#!/bin/bash
#./xilinx-reg-read-reader $DEV

DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"

if [ -z "$1" ]
then
    echo "No device specified. use xilinx0 as deault."
    DEV="xilinx0"
else
    DEV="$1"
fi

if [ -z "$2" ]
then
    echo "No show specified. use sh $DIR/table -15 -red,-green,-blue as deault."
    SHOW="sh $DIR/table -15 -red,-green,-blue"
else
    SHOW="$2"
fi

echo -e "---------------- Version Info ------------------
Ver Compile Date                                       \t 0x110002 \t $(printf "%x" $($DIR/reg-read $DEV 0x110002))
Ver Compile Version                                    \t 0x110001 \t $(printf '%x' $($DIR/reg-read $DEV 0x110001))
---------------- Fiber State Info ------------------
Fiber State                                            \t 0x110003 \t $(printf '%x' $($DIR/reg-read $DEV 0x110003))
16 DMA Ready | 4 RAW Ready                             \t 0x110004 \t $(printf '%x' $($DIR/reg-read $DEV 0x110004))
---------------- Level1/Level2 Info ------------------
Raw Data Upload Switch                                 \t 0x386    \t $(printf '%x' $($DIR/reg-read $DEV 0x386))
Level1 Decode Switch                                   \t 0x384    \t $(printf '%x' $($DIR/reg-read $DEV 0x384))
Level1 Restart Switch                                  \t 0x385    \t $(printf '%x' $($DIR/reg-read $DEV 0x385))
Level1 Time Consumed Initialization                    \t 0x38A    \t $(printf '%x' $($DIR/reg-read $DEV 0x38A))
Level1 Packet Loss Times                               \t 0x38B    \t $(printf '%x' $($DIR/reg-read $DEV 0x38B))
Level1 Packet Loss Times During Initialization         \t 0x38C    \t $(printf '%x' $($DIR/reg-read $DEV 0x38C))
Level1 Abnormal Package Status(1 Is Abnormal)          \t 0x3C4    \t $(printf '%x' $($DIR/reg-read $DEV 0x3C4))
Level1 Decode Condition(00 Is Valid)                   \t 0x3C5    \t $(printf '%x' $($DIR/reg-read $DEV 0x3C5))
Level1 Raw/Decoded Data FIFO Full                      \t 0x387    \t $(printf '%x' $($DIR/reg-read $DEV 0x387))
Level1 Assemble FIFO Full                              \t 0x389    \t $(printf '%x' $($DIR/reg-read $DEV 0x389))
Level1 Price Judge enable                              \t 0x38D    \t $(printf '%x' $($DIR/reg-read $DEV 0x38D))

Level2 Decode Switch                                   \t 0x110384 \t $(printf '%x' $($DIR/reg-read $DEV 0x110384))
Level2 Data Input Optical Port                         \t 0x110387 \t $(printf '%x' $($DIR/reg-read $DEV 0x110387))
Level2 Multi Address A                                 \t 0x1103AC \t $(printf '%x' $($DIR/reg-read $DEV 0x1103AC))
Level2 Multi Address B                                 \t 0x1103AD \t $(printf '%x' $($DIR/reg-read $DEV 0x1103AD))
Level2 Multi Port A                                    \t 0x1103AE \t $(printf '%x' $($DIR/reg-read $DEV 0x1103AE))
Level2 Multi Port B                                    \t 0x1103AF \t $(printf '%x' $($DIR/reg-read $DEV 0x1103AF))
Level2 Key2_Err|Key1_Err|State_next|State_current      \t 0x1103E9 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103E9))
Level2 Decode Vld Status(RAW0)                         \t 0x1103F0 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103F0))
Level2 Decode Vld Status(RAW1)                         \t 0x1103F1 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103F1))
Level2 Key1 Value(RAW0)                                \t 0x1103F2 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103F2))
Level2 Key1 Value(RAW1)                                \t 0x1103F3 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103F3))
Level2 Key2 Value(RAW0)                                \t 0x1103F4 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103F4))
Level2 Key2 Value(RAW1)                                \t 0x1103F5 \t $(printf '%x' $($DIR/reg-read $DEV 0x1103F5))
Level2 Seq_no_first                                    \t 0x11045B \t $(printf '%x' $($DIR/reg-read $DEV 0x11045B))
Level2 Seq_no_last                                     \t 0x11045C \t $(printf '%x' $($DIR/reg-read $DEV 0x11045C))
Level2 Seq_no_max                                      \t 0x11045D \t $(printf '%x' $($DIR/reg-read $DEV 0x11045D))
Level2 Subscribe All Enable                            \t 0x1107FD \t $(printf '%x' $($DIR/reg-read $DEV 0x1107FD))
Level2 Subscribe CP  Enable                            \t 0x1107FE \t $(printf '%x' $($DIR/reg-read $DEV 0x1107FE))
Level2 Subscribe SP/SPC Enable                         \t 0x1107FF \t $(printf '%x' $($DIR/reg-read $DEV 0x1107FF))
Level2 Subscribe Name1                                 \t 0x110800 \t $(printf '%x' $($DIR/reg-read $DEV 0x110800))
Level2 Subscribe Date1                                 \t 0x110801 \t $(printf '%x' $($DIR/reg-read $DEV 0x110801))
DMA_Store FIFO Full|Empty (/16bit)                     \t 0x1103EA \t $(printf '%x' $($DIR/reg-read $DEV 0x1103EA))
Top L1 FIFO Full|pF|Empty|pE (/2bit)                   \t 0x1103EB \t $(printf '%x' $($DIR/reg-read $DEV 0x1103EB))
Top L2 FIFO Full|pF|Empty|pE (/2bit)                   \t 0x1103EC \t $(printf '%x' $($DIR/reg-read $DEV 0x1103EC))
---------------- Package Counter ------------------
RAW0  Input                                            \t 0x11044D \t $(printf '%x' $($DIR/reg-read $DEV 0x11044D))
RAW1  Input                                            \t 0x11044E \t $(printf '%x' $($DIR/reg-read $DEV 0x11044E))
RAW0  Input  Error                                     \t 0x110465 \t $(printf '%x' $($DIR/reg-read $DEV 0x110465))
RAW1  Input  Error                                     \t 0x110466 \t $(printf '%x' $($DIR/reg-read $DEV 0x110466))
L1 Store FIFO1|0 (/16bit) back pressure                \t 0x1103ED \t $(printf '%x' $($DIR/reg-read $DEV 0x1103ED))
L2 Store FIFO1|0 (/16bit) back pressure                \t 0x1103EE \t $(printf '%x' $($DIR/reg-read $DEV 0x1103EE))
DMA0  Output SOP                                       \t 0x1104D1 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D1))
DMA0  Output EOP                                       \t 0x1104D2 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D2))
DMA1  Output SOP                                       \t 0x1104D3 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D3))
DMA1  Output EOP                                       \t 0x1104D4 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D4))
DMA2  Output SOP                                       \t 0x1104D5 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D5))
DMA2  Output EOP                                       \t 0x1104D6 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D6))
DMA3  Output SOP                                       \t 0x1104D7 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D7))
DMA3  Output EOP                                       \t 0x1104D8 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D8))
DMA4  Output SOP                                       \t 0x1104D9 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D9))
DMA4  Output EOP                                       \t 0x1104DA \t $(printf '%x' $($DIR/reg-read $DEV 0x1104DA))
DMA5  Output SOP                                       \t 0x1104DB \t $(printf '%x' $($DIR/reg-read $DEV 0x1104DB))
DMA5  Output EOP                                       \t 0x1104DC \t $(printf '%x' $($DIR/reg-read $DEV 0x1104DC))
DMA6  Output SOP                                       \t 0x1104DD \t $(printf '%x' $($DIR/reg-read $DEV 0x1104DD))
DMA6  Output EOP                                       \t 0x1104DE \t $(printf '%x' $($DIR/reg-read $DEV 0x1104DE))
DMA7  Output SOP                                       \t 0x1104DF \t $(printf '%x' $($DIR/reg-read $DEV 0x1104DF))
DMA7  Output EOP                                       \t 0x1104E0 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E0))
DMA8  Output SOP                                       \t 0x1104E1 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E1))
DMA8  Output EOP                                       \t 0x1104E2 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E2))
DMA9  Output SOP                                       \t 0x1104E3 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E3))
DMA9  Output EOP                                       \t 0x1104E4 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E4))
DMA10 Output SOP                                       \t 0x1104E5 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E5))
DMA10 Output EOP                                       \t 0x1104E6 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E6))
DMA11 Output SOP                                       \t 0x1104E7 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E7))
DMA11 Output EOP                                       \t 0x1104E8 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E8))
DMA12 Output SOP                                       \t 0x1104E9 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104E9))
DMA12 Output EOP                                       \t 0x1104EA \t $(printf '%x' $($DIR/reg-read $DEV 0x1104EA))
DMA13 Output SOP                                       \t 0x1104EB \t $(printf '%x' $($DIR/reg-read $DEV 0x1104EB))
DMA13 Output EOP                                       \t 0x1104EC \t $(printf '%x' $($DIR/reg-read $DEV 0x1104EC))
DMA14 Output SOP                                       \t 0x1104ED \t $(printf '%x' $($DIR/reg-read $DEV 0x1104ED))
DMA14 Output EOP                                       \t 0x1104EE \t $(printf '%x' $($DIR/reg-read $DEV 0x1104EE))
DMA15 Output SOP                                       \t 0x1104EF \t $(printf '%x' $($DIR/reg-read $DEV 0x1104EF))
DMA15 Output EOP                                       \t 0x1104F0 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104F0))
Arbitration l1 Raw    Data Output SOP                  \t 0x1104BD \t $(printf '%x' $($DIR/reg-read $DEV 0x1104BD))
Arbitration l1 Raw    Data Output EOP                  \t 0x1104BE \t $(printf '%x' $($DIR/reg-read $DEV 0x1104BE))
Arbitration l1 Decode Data Output SOP                  \t 0x1104BF \t $(printf '%x' $($DIR/reg-read $DEV 0x1104BF))
Arbitration l1 Decode Data Output EOP                  \t 0x1104C0 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104C0))
Arbitration l2 Raw    Data Output SOP                  \t 0x1104CD \t $(printf '%x' $($DIR/reg-read $DEV 0x1104CD))
Arbitration l2 Raw    Data Output EOP                  \t 0x1104CE \t $(printf '%x' $($DIR/reg-read $DEV 0x1104CE))
Arbitration l2 Decode Data Output SOP                  \t 0x1104CF \t $(printf '%x' $($DIR/reg-read $DEV 0x1104CF))
Arbitration l2 Decode Data Output EOP                  \t 0x1104D0 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104D0))

Level1 decode symbol order count                       \t 0x3BD    \t $(printf '%x' $($DIR/reg-read $DEV 0x3BD))
Level1 decode start count                              \t 0x3BE    \t $(printf '%x' $($DIR/reg-read $DEV 0x3BE))
Level1 next seq_no vld count                           \t 0x3BF    \t $(printf '%x' $($DIR/reg-read $DEV 0x3BF))
Level1 Unpacking Module Resolve Domain SOP             \t 0x3BB    \t $(printf '%x' $($DIR/reg-read $DEV 0x3BB))
Level1 Unpacking Module Resolve Domain EOP             \t 0x3BC    \t $(printf '%x' $($DIR/reg-read $DEV 0x3BC))
Level1 Assemble FIFO Writing WREN4 Valid               \t 0x393    \t $(printf '%x' $($DIR/reg-read $DEV 0x393))
Level1 Assemble Module Write FIFO                      \t 0x3B8    \t $(printf '%x' $($DIR/reg-read $DEV 0x3B8))
Level1 Assemble Module Read  FIFO                      \t 0x3AC    \t $(printf '%x' $($DIR/reg-read $DEV 0x3AC))

Min rx data bytes cnt                                  \t 0x3DF    \t $(printf '%x' $($DIR/reg-read $DEV 0x3DF))
Max rx data bytes cnt                                  \t 0x3DE    \t $(printf '%x' $($DIR/reg-read $DEV 0x3DE))
event sof         cnt                                  \t 0x370    \t $(printf '%x' $($DIR/reg-read $DEV 0x370))
event eof         cnt                                  \t 0x371    \t $(printf '%x' $($DIR/reg-read $DEV 0x371))
L1_dma_decode_data64 sof cnt                           \t 0x372    \t $(printf '%x' $($DIR/reg-read $DEV 0x372))
L1_dma_decode_data64 eof cnt                           \t 0x373    \t $(printf '%x' $($DIR/reg-read $DEV 0x373))


Level1 Assemble Error count                            \t 0x3AB    \t $(printf '%x' $($DIR/reg-read $DEV 0x3AB))
Level1 price_judge_err_negedge_count                   \t 0x3CA    \t $(printf '%x' $($DIR/reg-read $DEV 0x3CA))
Level1 last price low err count                        \t 0x3CB    \t $(printf '%x' $($DIR/reg-read $DEV 0x3CB))
Level1 last price high err count                       \t 0x3CC    \t $(printf '%x' $($DIR/reg-read $DEV 0x3CC))
Level1 ask price low err count                         \t 0x3CD    \t $(printf '%x' $($DIR/reg-read $DEV 0x3CD))
Level1 ask price high err count                        \t 0x3CE    \t $(printf '%x' $($DIR/reg-read $DEV 0x3CE))
Level1 bid price low err count                         \t 0x3CF    \t $(printf '%x' $($DIR/reg-read $DEV 0x3CF))
Level1 bid price high err count                        \t 0x3D0    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D0))
Level1 avg price low err count                         \t 0x3D1    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D1))
Level1 avg price high err count                        \t 0x3D2    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D2))

Level1 last price  err count                           \t 0x3D3    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D3))
Level1 ask price   err count                           \t 0x3D4    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D4))
Level1 bid price   err count                           \t 0x3D5    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D5))
Level1 avg price   err count                           \t 0x3D6    \t $(printf '%x' $($DIR/reg-read $DEV 0x3D6))

Level1 RAW0 Output SOP                                 \t 0x38E    \t $(printf '%x' $($DIR/reg-read $DEV 0x38E))
Level1 RAW0 Output EOP                                 \t 0x38F    \t $(printf '%x' $($DIR/reg-read $DEV 0x38F))
Level1 RAW1 Output SOP                                 \t 0x390    \t $(printf '%x' $($DIR/reg-read $DEV 0x390))
Level1 RAW1 Output EOP                                 \t 0x391    \t $(printf '%x' $($DIR/reg-read $DEV 0x391))
Level1 DMA64  Raw  Data FIFO Input   SOP               \t 0x394    \t $(printf '%x' $($DIR/reg-read $DEV 0x394))
Level1 DMA64  Raw  Data FIFO Input   EOP               \t 0x395    \t $(printf '%x' $($DIR/reg-read $DEV 0x395))
Level1 DMA64  Raw  Data FIFO Output  SOP               \t 0x396    \t $(printf '%x' $($DIR/reg-read $DEV 0x396))
Level1 DMA64  Raw  Data FIFO Output  EOP               \t 0x397    \t $(printf '%x' $($DIR/reg-read $DEV 0x397))
Level1 DMA256 Raw  Data 64_to_256    SOP               \t 0x1104B5 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104B5))
Level1 DMA256 Raw  Data 64_to_256    EOP               \t 0x1104B6 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104B6))
Level1 FIFO_READ   DMA256 Raw Data Output SOP          \t 0x1104B9 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104B9))
Level1 FIFO_READ   DMA256 Raw Data Output EOP          \t 0x1104BA \t $(printf '%x' $($DIR/reg-read $DEV 0x1104BA))

Level1 DMA64  Decode Data FIFO Input   SOP             \t 0x3C0    \t $(printf '%x' $($DIR/reg-read $DEV 0x3C0))
Level1 DMA64  Decode Data FIFO Input   EOP             \t 0x3C1    \t $(printf '%x' $($DIR/reg-read $DEV 0x3C1))
Level1 DMA64  Decode Data FIFO Outnput SOP             \t 0x3C2    \t $(printf '%x' $($DIR/reg-read $DEV 0x3C2))
Level1 DMA64  Decode Data FIFO Outnput EOP             \t 0x3C3    \t $(printf '%x' $($DIR/reg-read $DEV 0x3C3))
Level1 DMA256 Decode Data 64_to_256    SOP             \t 0x1104B7 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104B7))
Level1 DMA256 Decode Data 64_to_256    EOP             \t 0x1104B8 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104B8))
Level1 FIFO_READ DMA256 Decode Data Output SOP         \t 0x1104BB \t $(printf '%x' $($DIR/reg-read $DEV 0x1104BB))
Level1 FIFO_READ DMA256 Decode Data Output EOP         \t 0x1104BC \t $(printf '%x' $($DIR/reg-read $DEV 0x1104BC))

Level2 IP1 Valid(RAW0)                                 \t 0x11045E \t $(printf '%x' $($DIR/reg-read $DEV 0x11045E))
Level2 IP2 Valid(RAW0)                                 \t 0x11045F \t $(printf '%x' $($DIR/reg-read $DEV 0x11045F))
Level2 IP1 Valid(RAW1)                                 \t 0x110460 \t $(printf '%x' $($DIR/reg-read $DEV 0x110460))
Level2 IP2 Valid(RAW1)                                 \t 0x110461 \t $(printf '%x' $($DIR/reg-read $DEV 0x110461))
Level2 Decode Output SOF(RAW0)                         \t 0x110469 \t $(printf '%x' $($DIR/reg-read $DEV 0x110469))
Level2 Decode Output EOF(RAW0)                         \t 0x11046A \t $(printf '%x' $($DIR/reg-read $DEV 0x11046A))
Level2 Decode Output SOF(RAW1)                         \t 0x11046B \t $(printf '%x' $($DIR/reg-read $DEV 0x11046B))
Level2 Decode Output EOF(RAW1)                         \t 0x11046C \t $(printf '%x' $($DIR/reg-read $DEV 0x11046C))
Level2 DMA64  Decode Data FIFO Outnput SOP             \t 0x1104C3 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104C3))
Level2 DMA64  Decode Data FIFO Outnput EOP             \t 0x1104C4 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104C4))
Level2 DMA256 Decode Data 64_to_256    SOP             \t 0x1104C7 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104C7))
Level2 DMA256 Decode Data 64_to_256    EOP             \t 0x1104C8 \t $(printf '%x' $($DIR/reg-read $DEV 0x1104C8))
Level2 FIFO_READ DMA256 Decode Data Output SOP         \t 0x1104CB \t $(printf '%x' $($DIR/reg-read $DEV 0x1104CB))
Level2 FIFO_READ DMA256 Decode Data Output EOP         \t 0x1104CC \t $(printf '%x' $($DIR/reg-read $DEV 0x1104CC))

Level2 IP1 Valid Packages Before Optimal Mux(RAW0)     \t 0x110462 \t $(printf '%x' $($DIR/reg-read $DEV 0x110462))
Level2 IP2 Valid Packages Before Optimal Mux(RAW0)     \t 0x110463 \t $(printf '%x' $($DIR/reg-read $DEV 0x110463))
Level2 IP1+IP2 Valid Packages Before Optimal Mux(RAW0) \t 0x110464 \t $(printf '%x' $($DIR/reg-read $DEV 0x110464))
Level2 IP1 Valid Packages After Optimal Mux            \t 0x110457 \t $(printf '%x' $($DIR/reg-read $DEV 0x110457))
Level2 IP2 Valid Packages After Optimal Mux            \t 0x110458 \t $(printf '%x' $($DIR/reg-read $DEV 0x110458))
Level2 RAW0 Valid Packages After Optimal Mux           \t 0x110459 \t $(printf '%x' $($DIR/reg-read $DEV 0x110459))
Level2 RAW1 Valid Packages After Optimal Mux           \t 0x11045A \t $(printf '%x' $($DIR/reg-read $DEV 0x11045A))
Level2 Optimal Module Output SOF                       \t 0x110453 \t $(printf '%x' $($DIR/reg-read $DEV 0x110453))
Level2 Optimal Module Output EOF                       \t 0x110454 \t $(printf '%x' $($DIR/reg-read $DEV 0x110454))
Level2 MSG_CUT Module Output SOF                       \t 0x110455 \t $(printf '%x' $($DIR/reg-read $DEV 0x110455))
Level2 MSG_CUT Module Output EOF                       \t 0x110456 \t $(printf '%x' $($DIR/reg-read $DEV 0x110456))
Level2 DMA Output SOF                                  \t 0x11044F \t $(printf '%x' $($DIR/reg-read $DEV 0x11044F))
Level2 DMA Output EOF                                  \t 0x110450 \t $(printf '%x' $($DIR/reg-read $DEV 0x110450))
Level2 RAW Output SOF                                  \t 0x110451 \t $(printf '%x' $($DIR/reg-read $DEV 0x110451))
Level2 RAW Output EOF                                  \t 0x110452 \t $(printf '%x' $($DIR/reg-read $DEV 0x110452))" | ${SHOW}
